Dataram DTM65536B Datový list stáhnout pdf (Strana 15)

DTM65536B

2 GB - 240-Pin DDR2 Low Power FB-DIMM

Bit 5, Bit 4. TBD 0

Bit 6. High Temperature Self-Refresh - 1-Required

Bit 7. Double Refresh Requirement - 1-Supported

Tcasemax Delta.

Bit 3 ~ Bit 0. DT4R4W Delta, Subfield B: 0.4 °C - 0.8

Bit 7 ~ Bit 4. Tcasemax, Subfield A: 2 °C - 10

0x52

34 Thermal Resistance of SDRAM Package. °C/W

0x7A

SDRAM Case Temperature Rise from Ambient due to Activate-Precharge

minus 2.8 °C offset temperature (DT0). °C

Bit 1, Bit 0. Reserved 0

Bit 7 ~ Bit 2. DT0 - 6

0x50

SDRAM Case Temperature Rise from Ambient due to

Precharge/Quiet

Standby (DT2N/DT2Q). °C

4.7

0x2F

SDRAM Case Temperature Rise from Ambient due to

Precharge Power-Down (DT2P). °C

0.585

0x27

SDRAM Case Temperature Rise from Ambient due to Active

Standby (DT3N). °C

5.85

0x27

SDRAM Case Temperature Rise from Ambient due to Page

Open Burst

Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit).

Bit 0. DT4R4W Mode Bit, Subfield B: 0.4 °C 0

Bit 7 ~ Bit 1. DT4R, Subfield A: 0.4 °C - 15.2

0x4C

SDRAM Case Temperature Rise from Ambient due to

Burst Refresh (DT5B). °C

18.5 0x25

SDRAM Case Temperature Rise from Ambient due to Bank

Interleave Reads with Auto-Precharge (DT7). °C

0x28

42-74 Reserved

UNUSED

0x00

75 QR Control. 0x00

76 QR ODT control for Rank 0 and rank 1 Reads and writes. 0x00

77 QR ODT1 and ODT2 control for reads. 0x00

FBD ODT Definition for Rank 2 and 3

Bit 1, Bit 0. Rank 2 Data DRAM ODT - Disabled

Bit 3, Bit 2. Rank 2 Ecc DRAM ODT - Disabled

Bit 5, Bit 4. Rank 3 Data DRAM ODT - Disabled

Bit 7, Bit 6. Rank 3 Ecc DRAM ODT - Disabled

0x00

FBD ODT Definition for Rank 0 and 1

Bit 1, Bit 0. Rank 0 Data DRAM ODT - 150 Ohms

Bit 3, Bit 2. Rank 0 Ecc DRAM ODT - Disabled

Bit 5, Bit 4. Rank 1 Data DRAM ODT - 150 Ohms

Bit 7, Bit 6. Rank 1 Ecc DRAM ODT - Disabled

0x22

80 Reserved UNUSED 0x00

Channel Protocols Supported, Least Significant Byte

0x02

1 2 ... 10 11 12 13 14 15 16 17 18

DTM65536B 1

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